1. Field of the Invention
The present disclosure relates to the manufacturing of integrated circuits, in particular to the creation of a layout of an integrated circuit using electronic design automation techniques.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. Other types of circuit elements which may be present in integrated circuits include capacitors, diodes and resistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material, for example by means of damascene techniques. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate in and on which circuit elements, such as field effect transistors, capacitors, diodes and resistors, are formed. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal.
Due to the complexity of modern integrated circuits, in the design of integrated circuits, automated design techniques are typically employed.
The design of an integrated circuit may employ a number of steps. The steps may include the creation of a user specification that defines the functionality of the integrated circuit. The user specification may be the basis for the creation of a register transfer level description that models the integrated circuit in terms of a flow of signals between hardware registers and logical operations performed on those signals. The register transfer level description of the integrated circuit may then be used for the physical design of the integrated circuit, wherein a layout of the integrated circuit is created. The thus created layout may be the basis for the formation of photomasks that may be employed for patterning materials in the manufacturing of the integrated circuit.
The creation of a layout of an integrated circuit may be based on design rules that define constraints for the layout of the integrated circuit. Design rules may, for example, define spacings between circuit features of the integrated circuit, for example spacings between metal lines and/or contact vias, widths of circuit features, for example widths of metal lines, enclosures defining margins for circuit features that cover other circuit features, for example metal lines covering contact vias, or constraints relating to the relative arrangement of circuit features.
In the creation of a layout of an integrated circuit, the design rules may be modeled and provided to an layout construction tool that performs an automated layout construction process wherein the layout of the integrated circuit is created.
After the creation of the layout, the layout may be verified and/or optimized. In particular, design rule checks may be performed for confirming if the created layout fulfills all the design rules. If errors are found in the layout, the layout may be fixed. For this purpose, pattern matching techniques may be employed.
U.S. Pat. No. 8,429,582 discloses a method for automatic fixing of a layout. A first pattern from an electronic layout is identified. This may be done in accordance with a design rule checking error marker. One or more second patterns, which may provide a fixing of the error, may be identified from a database or other type of data structure of known “good” patterns, for example, in terms of design rule checking. The patterns may be grouped, and scoring processes may be performed to select one of a plurality of second patterns.
U.S. Pat. No. 8,418,105 discloses performing design rule checks and rule-based checks for double patterning technology compliance. If a design fails, an automated decomposition process decomposes the design, and a post-decomposed layout is generated, which is again checked for design rule and double patterning technology compliance. The layout may be scanned at error locations for similarities with pre-characterized patterns in a library of pre-characterized double patterning technology compliant patterns. When a match is found, an automated fixing of the problematic locations in the layout may be performed on the basis of the matching pattern.
In advanced techniques for the formation of integrated circuits, for example, techniques in accordance with the 20 nm technology node, a relatively large number of design rules may be involved. Furthermore, there may be design rules having a greater degree of complexity as compared to design rules that had to be considered in earlier technology nodes.
Existing algorithms for the layout of integrated circuits are typically optimized for a large variety of layout choices that are correct for a relatively small set of design rules. In contrast thereto, the design rules involved in advanced techniques for the formation of integrated circuits may constrain the space of correct layouts to a large degree, such that only a limited set of design constructs or patterns may remain for a desired layout situation. Furthermore, there may be design rules wherein modeling the design rules for the layout construction tool is difficult. Therefore, in some situations, a pessimistic modeling of design rules for automatic layout construction tools is employed, wherein design rules that cannot be modeled soundly for the layout construction tool are replaced with rules that can be modeled more easily, but lead to greater restrictions of the space of correct layouts than the original design rules.
Issues that may occur when conventional techniques for the creation of layouts are applied for integrated circuits that are to be formed using advanced process techniques may, thus, include pessimistic layouts, wherein an area required by the integrated circuit on a wafer and/or a speed of operation of the integrated circuit are less than optimal. Furthermore, conventional approaches may lead to a relatively large turn-around time, because a convergence of existing algorithms for the creation of layouts of integrated circuits may be difficult. Moreover, in some situations, a relatively large amount of manual fixing of the layout of an integrated circuit may be required.
In view of the situation described above, the present disclosure provides methods, computer systems and computer-readable storage media that may help to avoid or at least reduce some or all of the above-mentioned issues.